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STL60NH3LL
N-channel 30V - 0.0065 - 30A - PowerFLATTM (6x5) Ultra low gate charge STripFETTM Power MOSFET
General features
Type STL60NH3LL

VDSS 30V
RDS(on) <0.0085
ID 16A (2)
Improved die-to-footprint ratio Very low profile package (1mm max) Very low thermal resistance Very low gate charge Low threshold device
PowerFLATTM(6x5)
Description
This application specific Power MOSFET is the latest generation of STMicroelectronics unique "STripFETTM" technology. The resulting transistor is optimized for low on-resistance and minimal gate charge. The Chip-scaled PowerFLATTM package allows a significant board space saving, still boosting the performance.
Internal schematic diagram
Applications
Switching application
Order codes
Part number STL60NH3LL Marking L60NH3LL Package PowerFLATTM (6 x 5) Packaging Tape & reel
April 2006
Rev 3
1/13
www.st.com 13
Contents
STL60NH3LL
Contents
1 2 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Electrical characteristics (curves) ............................ 6
3 4 5
Test circuit
................................................ 9
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
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STL60NH3LL
Electrical ratings
1
Electrical ratings
Table 1.
Symbol VDS VGS ID
(1)
Absolute maximum ratings
Parameter Drain-source voltage (VGS = 0) Gate-source voltage Drain current (continuous) at TC = 25C Drain current (continuous) at TC = 100C Drain current (continuous) at TC = 25C Drain current (pulsed) Total dissipation at T C = 25C Total dissipation at T C = 25C Derating factor Value 30 16 30 30 16 64 60 4 0.03 -55 to 150 Unit V V A A A A W W W/C C
ID (1) ID(2) IDM
(3)
PTOT(1) PTOT(2)
Tj Tstg
Operating junction temperature Storage temperature
1. The value is rated according R thj-C and is limited by wire bonding. 2. This value is according Rthj-pcb 3. Pulse width limited by safe operating area
Table 2.
Symbol Rthj-case Rthj-pcb (1)
Thermal resistance
Parameter Thermal resistance junction-case (drain) Max Thermal resistance junction-pcb Max
2
Value 2.08 31.3
Unit C/W C/W
1. When mounted on FR-4 board of 1inch , 2 oz Cu, t<10sec
3/13
Electrical characteristics
STL60NH3LL
2
Electrical characteristics
(TCASE=25C unless otherwise specified) Table 3.
Symbol V(BR)DSS IDSS IGSS VGS(th) RDS(on)
On/off states
Parameter Drain-source breakdown voltage Zero gate voltage drain current (VGS = 0) Gate body leakage current (VDS = 0) Gate threshold voltage Static drain-source on resistance Test condictions ID = 250A, VGS= 0 VDS = Max rating, VDS = Max rating,@125C VDS = 16V VDS= V GS, ID = 250A VGS= 10V, ID= 8A VGS= 4.5V, ID= 8A 1 0.0065 0.0085 0.0075 0.0105 Min. 30 1 10 100 Typ. Max. Unit V A A nA V
Table 4.
Symbol Ciss Coss Crss Qg Qgs Qgd RG
Dynamic
Parameter Input capacitance Output capacitance Reverse transfer capacitance Total gate charge Gate-source charge Gate-drain charge Gate input resistance Test condictions Min. Typ. 1810 565 41 18 4.8 5.3 0.5 1.5 24 Max. Unit pF pF pF nC nC nC
VDS=25V, f = 1MHz, VGS=0
VDD = 15V, ID = 16A, VGS = 4.5V (see Figure 15) f=1 MHz Gate DC Bias = 0 Test signal level = 20mV open drain
3
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STL60NH3LL
Electrical characteristics
Table 5.
Symbol td(on) tr td(off) tf
Switching times
Parameter Turn-on delay time Rise time Turn-off delay time Fall time Test condictions VDD = 15V, ID = 8A RG= 4.7, VGS= 10V, (see Figure 14) VDD = 15V, ID = 8A RG= 4.7, VGS= 10V, (see Figure 14) Min. Typ. 8 65 30 20 Max. Unit ns ns ns ns
Table 6.
Symbol ISD ISDM VSD (1) trr Qrr IRRM
Source drain diode
Parameter Source-drain current Source-drain current (pulsed) Forward on voltage Reverse recovery time Reverse recovery charge Reverse recovery current ISD = 16A, VGS = 0 ISD = 16V, di/dt = 100A/s VDD = 20V, T j = 25C (see Figure 16) 22 32 1.9 Test condictions Min Typ. Max 16 64 1.3 Unit A A V ns nC A
1. Pulsed: Pulse duration = 300s, duty cycle 1.5%
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Electrical characteristics
STL60NH3LL
2.1
Figure 1.
Electrical characteristics (curves)
Safe operating area Figure 2. Thermal impedance
Figure 3.
Output characterisics
Figure 4.
Transfer characteristics
Figure 5.
Normalized BVDSS vs temperature
Figure 6.
Static drain-source on resistance
6/13
STL60NH3LL Figure 7. Gate charge vs gate-source voltage Figure 8.
Electrical characteristics Capacitance variations
Figure 9.
Normalized gate threshold voltage vs temperature
Figure 10. Normalized on resistance vs temperature
Figure 11. Source-drain diode forward characteristics
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Electrical characteristics
STL60NH3LL
Figure 12. Allowable Iav vs Time in Avalanche Figure 13. Allowable Iav vs Time in Avalanche
The previous curve gives the single pulse safe operating area for unclamped inductive loads under the following conditions: PD(AVE) =0.5*(1.3*BV DSS *I AV ) EAS(AR) =PD(AVE) *tAV
Where: IAV is the allowable current in avalanche PD(AVE) is the average power dissipation in avalanche (single pulse) tAV is the time in avalanche
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STL60NH3LL
Test circuit
3
Test circuit
Figure 15. Gate charge test circuit
Figure 14. Switching times test circuit for resistive load
Figure 16. Test circuit for inductive load Figure 17. Unclamped inductive load test switching and diode recovery times circuit
Figure 18. Unclamped inductive waveform
Figure 19. Switching time waveform
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Package mechanical data
STL60NH3LL
4
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com
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STL60NH3LL
Package mechanical data
PowerFLATTM (6x5) MECHANICAL DATA
mm. DIM. MIN. A A1 A3 b D D1 D2 E E1 E2 E4 e L 0.70 3.43 2.58 4.15 0.35 0.80 TYP 0.83 0.02 0.20 0.40 5.00 4.75 4.20 6.00 5.75 3.48 2.63 1.27 0.80 0.90 0.027 3.53 2.68 0.135 4.25 0.163 0.47 0.013 MAX. 0.93 0.05 MIN. 0.031 TYP. 0.032 0.0007 0.007 0.015 0.196 0.187 0.165 0.236 0.226 0.137 0.103 0.050 0.031 0.035 0.139 0.105 0.167 0.018 MAX. 0.036 0.0019 inch
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Revision history
STL60NH3LL
5
Revision history
Table 7.
Date 21-Jul-2004 05-Oct-2004 12-Apr-2006
Revision history
Revision 1 2 3 First Release Values Changed New template Changes
12/13
STL60NH3LL
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